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Sheet目录3881

173页 174页 175页 176页 [177页]178页 179页 180页 181页

PIC18F6585/8585/6680/8680

DS30491C-page 256

2004 Microchip Technology Inc.

19.6

A/D Conversions

Figure 19-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are cleared. A conversion is started after the follow-

ing instruction to allow entry into Sleep mode before the

conversion begins.

Figure 19-4 shows the operation of the A/D converter

after the GO bit has been set, the ACQT2:ACQT0 bits

are set to ‘010’ and selecting a 4 TAD acquisition time

before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will not be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

19.7

Use of the CCP2 Trigger

An A/D conversion can be started by the “special event

trigger” of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as ‘1011’ and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion

and the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition done before the “special

event trigger” sets the GO/DONE bit (starts a

conversion).

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D

module but will still reset the Timer1 (or Timer3)

counter.

FIGURE 19-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 19-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

Set GO bit

(Holding capacitor is disconnected)

Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

Conversion starts

(Holding capacitor continues

acquiring input)

TACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

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